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A67L9318/A67L8336
Preliminary
Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History
Rev. No.
0.0
512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM
History
Initial issue
Issue Date
July 13, 2005
Remark
Preliminary
PRELIMINARY
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A67L9318/A67L8336
Preliminary
Features
Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package
512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L9318, A67L8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous clock enable ( CEN ), byte write enables ( BW1, BW2 , BW3 , BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE ), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/ LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/ LD in High state. Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/ W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded. The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.
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Pin Configuration
OE ADV/ LD
BW4
BW3
BW2
BW1
CEN
VCC
VSS
CE2
CE2
CLK
R/W
A17
256K x 36
CE A6 A7
NC
A8 A8 82
BW2
BW1
VCC
CEN
VSS
CE2
CLK
CE2
R/W
CE
A18
NC
NC
NC
A6
A7
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
I/Oc8 I/Oc0 I/Oc1 VCCQ VSSQ I/Oc2 I/Oc3 I/Oc4 I/Oc5 VSSQ VCCQ I/Oc6 I/Oc7 VCC VCC VCC VSS I/Od0 I/Od1 VCCQ VSSQ I/Od2 I/Od3 I/Od4 I/Od5 VSSQ VCCQ I/Od6 I/Od7 I/Od8
NC NC NC VCCQ VSSQ NC NC I/Ob8 I/Ob7 VSSQ VCCQ I/Ob6 I/Ob5 VCC VCC VCC VSS I/Ob4 I/Ob3 VCCQ VSSQ I/Ob2 I/Ob1 I/Ob0 NC VSSQ VCCQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100
81
A9
512K x 18
OE ADV/ LD
A9
80 79 78 77 76 75 74 73 72 71 70 69
A10 NC NC VCCQ VSSQ NC I/Oa0 I/Oa1 I/Oa2 VSSQ VCCQ I/Oa3 I/Oa4 VSS VCC VCC ZZ I/Oa5 I/Oa6 VCCQ VSSQ I/Oa7 I/Oa8 NC NC VSSQ VCCQ NC NC NC
I/Ob8 I/Ob7 I/Ob6 VCCQ VSSQ I/Ob5 I/Ob4 I/Ob3 I/Ob2 VSSQ VCCQ I/Ob1 I/Ob0 VSS VCC VCC ZZ I/Oa7 I/Oa6 VCCQ VSSQ I/Oa5 I/Oa4 I/Oa3 I/Oa2 VSSQ VCCQ I/Oa1 I/Oa0 I/Oa8
A67L9318E A67L8336E
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
MODE MODE
A5
A4
A3
A2
A1
A0
A11
A12
A13
A14
A15
A16 A15
VCC
VSS
A10
A1
A11
A12
A13
A14
VSS
VCC
A16
A5
A4
A3
A2
A0
NC
NC
NC
NC
A17
NC
NC
NC
NC
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Block Diagram (256K X 36)
ZZ MODE MODE LOGIC
ADV/LD
CEN CLK
CLK LOGIC
BURST LOGIC ADDRESS COUNTER CLR
A0-A17
ADDRESS REGISTERS
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
9
BYTEa WRITE DRIVER BYTEb WRITE DRIVER BYTEc WRITE DRIVER BYTEd WRITE DRIVER
9
9 ADV/LD R/W BW1 BW2 BW3 BW4 WRITE REGISTRY & CONTROL LOGIC
9
256K x 9 x 4 MEMORY SENSE AMPS
9
9 ARRAY
OUTPUT REGISTERS & OUTPUT BUFFERS
I/Os
9
9
DATA-IN REGISTERS
DATA-IN REGISTERS
CE CE2 CE2
CHIP ENABLE LOGIC
PIPELINED ENABLE LOGIC
OUTPUT ENABLE LOGIC
OE
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Block Diagram (512K X 18)
ZZ MODE MODE LOGIC
ADV/LD
CEN CLK
CLK LOGIC
BURST LOGIC ADDRESS COUNTER CLR
A0-A18
ADDRESS REGISTERS
WRITE ADDRESS REGISTER
WRITE ADDRESS REGISTER
9 WRITE REGISTRY & CONTROL LOGIC
ADV/LD R/W BW1 BW2
BYTEa WRITE DRIVER
9 512K X 9 X 2 MEMORY SENSE AMPS OUTPUT REGISTERS & OUTPUT BUFFERS I/OS
9
BYTEb WRITE DRIVER
9
ARRAY
DATA-IN REGISTERS
DATA-IN REGISTERS
CE CE2 CE2
CHIP ENABLE LOGIC
PIPELINED ENABLE LOGIC
OUTPUT ENABLE LOGIC
OE
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Pin Description
Pin No. LQFP (X18) 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 83 83 LQFP (X36) 37 36 35, 34, 33, 32, 100, 99, 82, 81, 45, 46, 47, 48, 49, 50, 83 44 93 ( BW1) 94 ( BW2 ) 93 ( BW1) 94 ( BW2 ) 95 ( BW3 ) 96 ( BW4 ) A0 A1 A2 - A9 A11 - A17 A18 A10
BW1 BW2 BW3 BW4
Symbol
Description
Synchronous Address Inputs : These inputs are registered and must meet the setup and hold times around the rising edge of CLK. A0 and A1 are the two lest significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Synchronous Byte Write Enables : These active low inputs allow individual bytes to be written when a WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK. BYTE WRITEs need to be asserted on the same cycle as the address, BWs are associated with addresses and apply to subsequent data. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; BW4 controls I/Od pins. Clock: This signal registers the address, data, chip enables, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock are rising edge. Synchronous Chip Enable : This active low input is used to enable the device. This input is sampled only when a new external address is loaded (ADV/ LD LOW). Synchronous Chip Enable : This active low input is used to enable the device and is sampled only when a new external address is loaded (ADV/ LD LOW). This input can be used for memory depth expansion. Synchronous Chip Enable : This active high input is used to enable the device and is sampled only when a new external address is loaded (ADV/ LD LOW). This input can be used for memory depth expansion.
89
89
CLK
98
98
CE
92
92
CE2
97
97
CE2
86
86
OE
Output Enable : This active low asynchronous input enables the data I/O output drivers. Synchronous Address Advance/Load : When HIGH, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. When HIGH, R/ W is ignored. A LOW on this pin permits a new address to be loaded at CLK rising edge. Synchronous Clock Enable : This active low input permits CLK to propagate throughout the device. When HIGH, the device ignores the CLK input and effectively internally extends the previous CLK cycle. This input must meet setup and hold times around the rising edge of CLK.
85
85
ADV/ LD
87
87
CEN
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Pin Description (continued)
Pin No. LQFP (X18) LQFP (X36) Symbol Description
64
64
ZZ
Snooze Enable : This active high asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. Read/Write : This active input determines the cycle type when ADV/ LD is LOW. This is the only means for determining READs and WRITEs. READ cycles may not be converted into WRITEs (and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Full bus width WRITEs occur if all byte write enables are LOW. SRAM Data I/O : Byte "a" is I/Oa pins; Byte "b" is I/Ob pins; Byte "c" is I/Oc pins; Byte "d" is I/Od pins. Input data must meet setup and hold times around CLK rising edge.
88
88
R/ W
74, 73, 72, 69, 68, 63, 62, 59, 58, 24, 23, 22, 19, 18 13, 12, 9, 8
51, 52, 53, 56, 57, 58, 59, 62, 63 68, 69, 72, 73, 74, 75, 78, 79, 80 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 31
I/Oa I/Ob I/Oc I/Od
31
MODE
Mode : This input selects the burst sequence. A LOW on this pin selects linear burst. NC or HIGH on this pin selects interleaved burst. Do not alter input state while device is operating. No Connect : These pins can be left floating or connected to GND to minimize thermal impedance.
1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42,43 51, 52, 53, 56, 57, 75, 78, 79, 95, 96 15, 41, 65, 91
38,39,42,43
NC
15, 41, 65, 91
VCC
Power Supply : See DC Electrical Characteristics and Operating Conditions for range. These pins do not have to be connected directly to VCC as long as the input voltage is VIH. This input is not connected to VCC bus internally. Isolated Output Buffer Supply : See DC Electrical Characteristics and Operating Conditions for range. Ground : GND. Isolated Output Buffer Ground
14, 16, 66
14, 16, 66
VCC
4, 11, 20, 27, 54, 61, 70, 77 17, 40, 90 5,10,21,26, 55,60,71,76
4, 11, 20, 27, 54, 61, 70, 77 17, 40, 90 5,10,21,26, 55,60,71,76
VCCQ
VSS VSSQ
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Truth Table (Notes 5 - 7)
Operation Address Used None
CE CE2 CE2
ZZ
Deselected Cycle, H X X L X X X L LH High-Z Power-down Deselected Cycle, None X H X L L X X X L LH High-Z Power-down Deselected Cycle, None X X L L L X X X L LH High-Z Power-down Continue Deselect None X X X L H X X X L LH High-Z 1 Cycle READ Cycle External L L H L L H X L L LH Q (Begin Burst) READ Cycle Next X X X L H X X L L LH Q 1,7 (Continue Burst) NOP/Dummy READ External L L H L L H X H L LH High-Z 2 (Begin Burst) Dummy READ Next X X X L H X X H L LH High-Z 1,2,7 (Continue Burst) WRITE Cycle External L L H L L L L X L LH D 3 (Begin Burst) WRITE Cycle Next X X X L H X L X L LH D 1,3,7 (Continue Burst) NOP/WRITE Abort None L L H L L L H X L LH High-Z 2,3 (Begin Burst) WRITE Abort Next X X X L H X H X L LH High-Z 1,2,3,7 (Continue Burst) IGNORE Clock Edge Current X X X L X X X X H LH 4 (Stall) SLEEP Mode None X X X H X X X X X X High-Z Notes: 1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first. 2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE Abort means a WRITE command is given, but no operation is performed. 3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their requirements. 4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock Edge cycle. 5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals ( BW1, BW2 , BW3 and BW4 ) are HIGH. BWx = L means one or more byte write signals are LOW. 6. BW1enables WRITEs to Byte "a" (I/Oa pins); BW2 enables WRITEs to Byte "b" (I/Ob pins); BW3 enables WRITEs to Byte "c" (I/Oc pins); BW4 enables WRITEs to Byte "d" (I/Od pins). 7. The address counter is incremented for all Continue Burst cycles.
ADV/ LD L
R/ W
BWx
OE
CEN
CLK
I/O
Notes
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Partial Truth Table for READ/WRITE Commands (X18)
Operation R/ W
BW1 BW2
READ WRITE Byte "a" WRITE Byte "b" WRITE all bytes WRITE Abort/NOP
H L L L L
X L H L H
X H L L H
Note : Using and BYTE WRITE(s), any one or more bytes may be written.
Partial Truth Table for READ/WRITE Commands (X36)
Operation R/ W
BW1 BW2
BW3
BW4
READ WRITE Byte "a" WRITE Byte "b" WRITE Byte "c" WRITE Byte "d" WRITE all bytes WRITE Abort/NOP
H L L L L L L
X L H H H L H
X H L H H L H
X H H L H L H
X H H H L L H
Note : Using R/ W and BYTE WRITE(s), any one or more bytes may be written.
Linear Burst Address Table (MODE = LOW)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10
Interleaved Burst Address Table (MODE = HIGH or NC)
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00
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Absolute Maximum Ratings*
Power Supply Voltage (VCC) . . . . . . . . . . -0.3V to +4.6V Voltage Relative to GND for any Pin Except VCC (Vin, Vout) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Operating Temperature (Topr) . . . . . . . . . . . 0C to 70C Storage Temperature (Tbias) . . . . . . . . . . -10C to 85 C Storage Temperature (Tstg) . . . . . . . . . . -55C to 125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics and Operating Conditions
(0C TA 70C, VCC, VCCQ = +3.3V 5% unless otherwise noted)
Symbol Parameter Conditions Min. Max. Unit Note
VIH VIL ILI ILO
Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current 0V VIH VCC Output(s) disabled, 0V VIN VCC
1.7 -0.3 -2.0 -2.0
VCC+0.3 0.8 TBD TBD
V V
A A
1,2 1,2
VOH VOL VCC VCCQ
Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply
IOH = -1.0mA IOL = 1.0mA
2.0 0.4 3.135 3.135 3.465 VCC
V V V V
1,3 1,3 1 1,4
Capacitance
Symbol Parameter Conditions Typ. Max. Unit Note
CI CO CA
Control Input Capacitance Input/Output Capacitance (I/O) Address Capacitance
TA = 25C; f = 1MHz VCC = 3.3V
3 4 3
4 5 3.5
pF pF pF
6 6 6
Note : 1. All voltages referenced to VSS (GND). 2. Overshoot : VIH +4.6V for t tKHKH/2 for I 20mA Undershoot : VIL -0.7V for t tKHKH/2 for I 20mA Power-up : VIH +3.465V and VCC 3.135V for t 200ms 3. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 4. VCC and VCCQ can be externally wired together to the same power supply. 5. This parameter is sampled.
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ICC Operating Condition and Maximum Limits
Max. Symbol Parameter -2.6 -2.8 -3.2 -3.5 -3.8 -4.2 Unit Conditions
ICC
Power Supply Current : Operating
TBD
TBD
TBD
TBD
TBD
TBD
mA
Device selected; All inputs VIL or VIH; Cycle time tKC (MIN); VCC = MAX; Outputs open Device deselected; VCC = MAX; All inputs VSS+0.2 or VCC0.2; Cycle time tKC (MIN) Device deselected; VCC = MAX; All inputs VSS+0.2 or VCC0.2; All inputs static; CLK frequency=0 ZZ 0.2V Device deselected; VCC = MAX; All inputs VIL; or VIH; All inputs static; CLK frequency=MAX ZZ VCC-0.2V ZZ VIH
ISB
Standby
TBD
TBD
TBD
TBD
TBD
TBD
mA
ISB1
Standby
TBD
TBD
TBD
TBD
TBD
TBD
mA
ISB2
Standby
TBD
TBD
TBD
TBD
TBD
TBD
mA
ISB2Z
SLEEP Mode
TBD
TBD
TBD
TBD
TBD
TBD
mA
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AC Characteristics (Note 4) (0C TA 70C, VCC = +3.3V 5%)
-2.6 Symbol Parameter
Min Max Min Max Min Max Min Max Min Max Min Max
-2.8
-3.2
-3.5
-3.8
-4.2 Unit Note
Clock tKHKH tKF tKHKL tKLKH Clock cycle time Clock frequency Clock HIGH time Clock LOW time 4.0 1.7 1.7 250 4.4 2.0 2.0 227 5.0 2.0 2.0 200 6.0 2.2 2.2 166 6.7 2.5 2.5 150 7.5 3.0 3.0 133 ns MH ns ns
Output Times tKHQV tKHQX tKHQX1 tKHQZ tGLQV tGLQX tGHQZ Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z 1.5 1.5 1.5 0 2.6 2.6 2.6 2.6 1.5 1.5 1.5 0 2.8 2.8 2.8 2.8 1.5 1.5 1.5 0 3.2 3.0 3.2 3.0 1.5 1.5 1.5 0 3.5 3.0 3.5 3.0 1.5 1.5 1.5 0 3.8 3.0 3.8 3.0 1.5 1.5 1.5 0 4.2 3.5 4.2 3.5 ns ns ns ns ns ns ns 1,2,3 1,2,3 4 1,2,3 1,2,3
OE to output valid OE to output in Low-Z OE to output in High-Z
Setup Times tAVKH tEVKH tCVKH tDVKH Address Clock enable ( CEN ) Control signals Data-in 1.2 1.2 1.2 1.2 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns 5 5 5 5
Hold Times tKHAX tKHEX tKHCX tKHDX Address Clock enable ( CEN ) Control signals Data-in 0.3 0.3 0.3 0.3 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 5 5 5 5
Notes: 1. This parameter is sampled. 2. Output loading is specified with C1=5pF as in Figure 2. 3. Transition is measured 200mV from steady state voltage. 4. OE can be considered a "Don't Care" during WRITE; however, controlling OE can help fine-tune a system for turnaround timing. 5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADV/ LD is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK (when ADV/ LD is LOW) to remain enabled.
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AC Test Conditions
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 1.0ns 1.25V 1.25V See Figures 1 and 2
+3.3V Q Q ZO=50 50 353 5pF 319
VT=1.5V
Figure 1 Output Load Equivalent
Figure 2 Output Load Equivalent
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SLEEP Mode
SLEEP Mode is a low current "Power-down" mode in which the device is deselected and current is reduced to ISB2Z. This duration of SLEEP Mode is dictated by the length of time the ZZ is in a HIGH state. After entering SLEEP Mode, all inputs except ZZ become disabled and all outputs go to High-Z. The ZZ pin is asynchronous, active high input that causes the device to enter SLEEP Mode. When the ZZ pin becomes logic HIGH, ISB2Z is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP Mode is not guaranteed to successfully complete. Therefore, SLEEP Mode (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting SLEEP Mode during tRZZ, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP Mode.
SLEEP Mode Electrical Characteristics
(VCC, VCCQ = +3.3V5%)
Symbol Parameter Conditions Min. Max. Unit Note
ISB2Z tZZ tRZZ tZZI tRZZI
Current during SLEEP Mode ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current
ZZ VIH
0 0 0
60 2(tKHKH) 2(tKHKH) 2(tKHKH)
mA ns ns ns ns 1 1 1 1
Note : 1. This parameter is sampled.
SLEEP Mode Waveform
CLK
tZZ tRZZ
ZZ
tZZI
ISUPPLY
IISB2Z tRZZI
ALL INPUTS (except ZZ)
DESELECT or READ Only
Output (Q)
High-Z
: Don't Care
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READ/WRITE Timing
1 CLK tEVKH CEN tCVKH CE ADV/ LD R/W tKHCX tKHEX tKHKL tKLKH 2 tKHKH 3 4 5 6 7 8 9 10
BWx
ADDRESS tAVKH
A1 tKHAX
A2
A3
A4 tKHQV
A5
A6
A7
tDVKH I/O D(A1)
tKHDX D(A2)
tKHQX1 D(A2+1)
tKHQX Q(A3)
tGLQV Q(A4) tGHQZ tGLQX
Q(A4+1)
tKHQZ D(A5) tKHQX Q(A6)
OE COMMAND BURST WRITE D(A2+1) READ Q(A4) BURST READ Q(A4+1)
WRITE D(A1)
WRITE D(A2)
READ Q(A3)
WRITE D(A5)
READ Q(A6) : Don't Care
WRITE D(A7)
DESELECT
: Undefined
Note : 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BRST operations are optional. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated the most current data is used. The most recent data may be from the input data register.
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A67L9318/A67L8336
NOP, STALL and Deselect Cycles
1 CLK 2 3 4 5 6 7 8 9 10
CEN
CE ADV/ LD R/W
BWx
ADDRESS
A1
A2
A3
A4
A5 tKHQZ
I/O
D(A1)
Q(A2)
Q(A3)
D(A4)
Q(A5) tKHQX
COMMAND
WRITE D(A1)
READ Q(A2)
STALL
READ Q(A3)
WRITE D(A4)
STALL
NOP
READ Q(A5) : Don't Care
DESELECT
CONTINUE DESELECT
: Undefined
Note : 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CEN being used to create a "pause." A WRITE is
not performed during this cycle. 2. For this waveform, ZZ and OE are tied LOW. 3. CE represents three signals. When CE = 0, it represents CE = 0, CE2 = 0, CE2 = 1. 4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most recent data may be from the input data register.
PRELIMINARY
(July, 2005, Version 0.0)
16
AMIC Technology, Corp.
A67L9318/A67L8336
Ordering Information
Part No. Configure Cycle Time / Access Time Package
A67L9318E-4.2 A67L9318E-4.2F A67L9318E-3.8 A67L9318E-3.8F A67L9318E-3.5 A67L9318E-3.5F 512K X 18 A67L9318E-3.2 A67L9318E-3.2F A67L9318E-2.8 A67L9318E-2.8F A67L9318E-2.6 A67L9318E-2.6F A67L8336E-4.2 A67L8336E-4.2F A67L8336E-3.8 A67L8336E-3.8F A67L8336E-3.5 A67L8336E-3.5F 256K X 36 A67L8336E-3.2 A67L8336E-3.2F A67L8336E-2.8 A67L8336E-2.8F A67L8336E-2.6 A67L8336E-2.6F
7.5ns / 4.2ns 7.5ns / 4.2ns 6.7ns / 3.8ns 6.7ns / 3.8ns 6.0ns / 3.5ns 6.0ns / 3.5ns 5.0ns / 3.2ns 5.0ns / 3.2ns 4.4ns / 2.8ns 4.4ns / 2.8ns 4.0ns / 2.6ns 4.0ns / 2.6ns 7.5ns / 4.2ns 7.5ns / 4.2ns 6.7ns / 3.8ns 6.7ns / 3.8ns 6.0ns / 3.5ns 6.0ns / 3.5ns 5.0ns / 3.2ns 5.0ns / 3.2ns 4.4ns / 2.8ns 4.4ns / 2.8ns 4.0ns / 2.6ns 4.0ns / 2.6ns
100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP 100L LQFP 100L Pb-Free LQFP
PRELIMINARY
(July, 2005, Version 0.0)
17
AMIC Technology, Corp.
A67L9318/A67L8336
Package Information LQFP 100L Outline Dimensions
unit: inches/mm
HE E
80 51
A2
A1 y D
81
50
HD D
100
31
1
30
e
b
c
Symbol A1 A2 b c HE E HD D e L L1 y
Dimensions in inches Min. 0.002 0.053 0.009 0.004 Nom. 0.055 0.012 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.024 0.039 REF 0 3.5 0.004 7 0.030 Max. 0.006 0.057 0.015 0.008
Dimensions in mm Min. 0.05 1.35 0.22 0.09 Nom. 1.40 0.30 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.60 1.00 REF 0 3.5 0.10 7 0.75 Max. 0.15 1.45 0.38 0.20
Notes: 1. Dimensions D and E do not include mold protrusion. 2. Dimensions b does not include dambar protrusion. Total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
L
L1
PRELIMINARY
(July, 2005, Version 0.0)
18
AMIC Technology, Corp.

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